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TECHNICAL NOTE
Single-chip Type with Built-in FET Switching Regulator Series
2-output High-efficiency Step-down Switching Regulators with Built-in Power MOSFET
BD9302FP
Description The BD9302FP is a 2-channel step-down switching regulator controller with a 2.5-MHz, 2-A power switch and available for 2.5-MHz high speed switching operation, which facilitates settings of switching frequency with external resistance, supporting for a wide input voltage range of 6 to 18 V. Furthermore, due to a low reference voltage of 0.6 V, this BD9302FP is an L/C best suited to high-voltage input/low-voltage output applications, for example, to step down a voltage from 12 V to 1.2 V.
Features 1) 2) 3) 4) 5) 6) 7) A wide input voltage range of 6 V to 18 V Easy switching frequency setting in the range of 200 k to 2.5 MHz. Two built-in power switches of 0.4 , 2 A. 180 phase shift Built-in Under Voltage Lock Out circuit Built-in overcurrent protection circuit Built-in Thermal Shutdown circuit
Use Power supply for DPS requiring two power sources ADSL modem/plasma display Audio devices
Dec. 2008
Absolute maximum ratings (Ta=25C)
Item Power supply voltage Power dissipation Operating temperature Storage temperature Output current Maximum junction temperature Symbol Vcc Pd Topr Tstg Io Tjmax Rating 20 1450* -40 ~ +85 -55 ~ +150 2** 150 Unit
V mW
C C A C
* Should be derated by 11.6 mW/C at Ta=25C or more. When mounted on a glass epoxy PCB of 70701.6 mm) ** Should not exceed Pd-value.
Recommended operating range (Ta=25C)
Item Power supply voltage Output current Timing resistance Oscillation frequency Symbol Vcc Io RT Fosc Limits Typ 12 - - - Unit V A k kHz
Min 6 - 10 100
Max 18 1.8 100 2500
Electrical characteristics Electrical characteristics (Unless otherwise specified, Ta=25C, Vcc=12 V, RT=10 k)
Item [Triangular wave oscillator block] Oscillation frequency Frequency variation Overcurrent limit FOSC FDVO Isw 1800 - 2 2000 1 4 3.3 3.0 10 1.7 1.95 - Symbol Limits Min Typ Max Unit Conditions
2200 - 6 3.6 3.3 14 5 2.15 0.3
kHz % A V V uA mA V V
RT=10k ~ 18V
*
[Overcurrent protection circuit block] [Under-voltage malfunction prevention circuit block] 3.0 Upper limit threshold voltage VtH 2.7 Lower limit threshold voltage VtL [Soft start circuit block] Source current Sink current Clamp voltage Shutdown voltage Isso ISSI Vcl VSDWN 6 0.6 1.75 -
Vss=1V Vss=1V, Vcc=3V Vcc=3V
Not designed for radiation resistance. * Design guarantee (No 100% pre-shipment inspections are conducted.)
2/16
Electrical characteristics Electrical characteristics (Unless otherwise specified, Ta=25C, Vcc=12 V, RT=10 k)
Item [Error amplifier block] Input bias current Voltage gain COMP maximum output voltage COMP minimum output voltage Output sink current Output source current Feedback voltage [Output block] Upper-side ON resistance Low-side ON resistance OFF current [Total device] Average supply current ICC Ronh Ronl IOFF IIB AV VOH VOL IOI IOO VFB Symbol Min Limits Typ 0.4 200 1.95 0.8 2 Max 1 Unit Conditions
- -
1.75
uA V/V V V mA mA V mA mA ICOMP= -0.1mA ICOMP=0.1mA VFB=0.8V VFB=0.4V Buffer Io=1A* Io=20mA* SW=0V RT=1.0V
- -
1.0 4
-
1
-8
0.588
-4
0.600 0.4 2 0.2
-1
0.612 0.6 3 0.4
- -
0.1
-
5
-
Not designed for radiation resistance. * Design guarantee (No 100% pre-shipment inspections are conducted.)
Measurement circuit diagram
10pF 30k NULL AMP
+ V
-
V
A
PGND1 COMP1
V A
SW1L SW1 SW1 BOOT1 PVcc PVcc 1uF
A
30k
100k 1k 0.6V 1000pF
FB1
1V 10K
10k 1000pF
A
RT NC SS1
V
5V
1V 10pF 30k 30k
A V A
12V 1V
V
A
Vcc SS2 NC FB2 COMP2 PVcc PVcc BOOT2 SW2 SW2 SW2L 1uF
A
NULL AMP 100k 1k 0.6V 1000pF
V +
-
5V
10k 1000pF
V A
GND PGND2
Fig. 1 Typical measurement circuit
3/16
Reference characteristics data
0.66 0.65 0.64 0.63 0.62 0.61 0.60 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 0.51 0.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85 AMBIENT TEMPERATURE : Ta [C] 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85 AMBIENT TEMPERATURE : Ta [C] 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 SWITCHING FREQUENCY : FSW [kHz]
FEED BACK VOLTAGE : VFB [V]
CIRCUIT CURRENT : ICC [mA]
85C
-40C
25C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 INPUT VOLTAGE : VCC [V]
Fig.2 Feedback voltage - Ambient temperature
0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85 AMBIENT TEMPERATURE : Ta [C] SWL ON RESISTANCE : RONL [] SW ON RESISTANCE : RONH []
Fig.3 Switching frequency - Ambient temperature
3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85 AMBIENT TEMPERATURE : Ta [C] SWITCHING FREQUENCY : FSW [kHz] 100000
Fig.4 Power supply voltage - Circuit current
10000
1000
100
10
10 100 TIMING RESISTANCE : RT [k]
Fig.5 SW ON resistance - Ambient temperature
100 90 80 MAX DUTY [%] 70 60 50 40 30 20 10 0 200 1000 2000 SWITCHING FREQUENCY : FSW [kHz] SWITCHING FREQUENCY : FSW [kHz] 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0
Fig.6 SWL ON resistance - Ambient temperature
100 90 80 EFFICIENCY : h [%] 70 60 50 40 30 20 10 67 8 9 10 11 12 13 14 15 16 17 18 INPUT VOLTAGE : VCC [V] 0
Fig.7 Setting resistance - Switching frequency
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 OUTPUT CURRENT : IO [A]
Fig.8 Switching frequency - MAX Duty
Fig.9 Switching frequency - Power supply voltage
Fig.10 Output current - Efficiency
(*) The data shown above represent real values sampled but not guarantee values.
4/16
Reference characteristics data
100 90 80 EFFICIENCY : h [%] EFFICIENCY : h [%] 70 60 50 40 30 20 10 0 6 7 8 9 10 11 12 13 14 15 16 17 18 INPUT VOLTAGE : VCC [V] 100 90 DELAY TIME : TV01 [ms] 80 70 60 50 40 30 20 10 0 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 SWITCHING FREQUENCY : FSW [kHz] 0 0.01 0.10 SS CAPACITOR : CSS [F] 1.00 100
10
1
Fig.11 Power supply voltage - Efficiency
Fig.12 Switching frequency - Efficiency
Fig.13 Set capacitance - Delay time
12V INPUT VOLTAGE OUTPUT CURRENT OUTPUT CURRENT
1.47ms OUTPUT VOLTAGE
2.5V OUTPUT VOLTAGE (AC) OUTPUT VOLTAGE (AC)
Fig.14 Startup waveform
Fig.15 Load transient response No. 1
Fig.16 Load transient response No. 2
Application measurement circuit diagram
33pF
100 3300pF k 20k 10H Vo1=3.3V
BD9302FP
22 51k k 0.1F
0.1F
10F
10F
Vcc 12V
0.1F 20k 30k 30 k 3300 pF 33 pF
0.1F
10H Vo2=1.2V 10F
Fig.17 Application measurement circuit diagram
(*) The data shown above represent real values sampled but not guarantee values.
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Pin assignment
PGND1 COMP1 FB1 RT N.C. SS1/SDWN Fin Fin VCC SS2/SDWN N.C. 7 8 9 19 PVCC 18 PVCC 17 BOOT2 16 SW2 15 SW2 14 SW2L 1 2 3 4 5 6 25 SW1L
Block diagram
PGND1
24 SW1 23 SW1 22 BOOT1 21 PVCC 20 PVCC
1
25 SW1L
COMP1
2 0.6V + ERR
OCP Current Sense
24 SW1
FB1
3
23 SW1
RT N.C. SS1/SDWN VCC
4 5 6
slope +PWM
DRV2 SDWN Set DRV1 Reset SDWN
22 BOOT1
21 PVCC
FB2 10 COMP2 11 GND 12 PGND2 13
7 UVLO TSD 5V OSC
20 PVCC
VREF SS2/SDWN 8
Internal Bias
19 PVCC
N.C.
9 0.6V Set ERR PWM +Reset + -
SDWN DRV1
18 PVCC
FB2 10
DRV2 SDWN
17 BOOT2
COMP2 11
slope OCP
Current Sense
16 SW2
GND 12
15 SW2
PGND2 13
14 SW2L
Fig.18 Pin assignment / Block diagram Pin assignment / functions
Pin No. 1 2 3 4 5 6 Pin name Function Ground Error amplifier output Error amplifier inverting input Frequency setting resistor connection N.C. Soft start capacitor connection (Shutdown at Low) 7 8 Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name PGND2 SW2L SW2 SW2 BOOT2 Pvcc Pvcc Pvcc Pvcc BOOT1 SW1 SW1 SW1L Ground Function
TOP VIEW
PGND1 COMP1 FB1 RT
Switching output 2 (Low side) Switching output 2 Switching output 2 Boot capacitor connection Power supply input Power supply input Power supply input Power supply input Boot capacitor connection Switching output 1 Switching output 1 Switching output 1 (Low side)
-
SS1/SDWN
VCC SS2/SDWN
Power supply input Soft start capacitor connection (Shutdown at Low)
9 10 11 12
-
FB2 COMP2 GND
N.C. Error amplifier inverting input Error amplifier output Ground
6/16
33pF
100k
PGND1
1
25
SW1L
3300 pF COMP1 20k FB1 22k RT 51k
2 0.6V + ERR
OCP Current Sense
24
SW1 10 H VO : 3.3V 10F
3
23
SW1
4
slope +PWM
N.C. 5 SS1/SDWN 0.1F VCC VCC VREF SS2/SDWN 0.1F N.C. 9 0.6V FB2 30 k 30 k 33 pF COMP2 3300 20 pF k GND 11 10 + ERR 8 6 7
DRV2 SDWN Set DRV1 Reset SDWN
0.1F BOOT1 22
21
PVCC
20 Internal Bias UVLO TSD OSC
PVCC
5V 19 PVCC
10 F
VCC
Set Reset PWM +slope
SDWN DRV1
18
PVCC
DRV2 SDWN
17
BOOT2 0.1 F 10 H 10 F
Current Sense OCP
16
SW2
VO : 1.2V
12 PGND2
15
SW2
13
14
SW2L
Fig.19 Typical application circuit u Error amplifier (ERR) block The ERR block is a circuit used to compare between the 0.6-V reference voltage and the feedback voltage of output voltage. The COMP voltage, a result of this comparison, determines the switching Duty. Furthermore, soft start function is activated with the SS voltage while in startup operation. Consequently, the COMP voltage is limited to the SS voltage. u Oscillator (OSC) block The OSC block is a block to determine the switching frequency through the RT pin, which is settable in the range of 100 kHz to 2500 kHz. u SLOPE block The SLOPE block is a block to generate a triangular wave from the clock generated with the OSC and then to transmit the triangular wave to the PWM comparator. u PWM block The PWM block is used to make comparison between the output COMP voltage of the error amplifier block and the triangular wave of the SLOPE block, thus determining the switching Duty. The switching duty is limited with the maximum duty ratio, which is internally determined, and will not reach 100%. u Reference voltage (UREF) block The UREF block is a block to generate a 2.9-V internal reference voltage. u Protection circuit (UVLO/TSD) block The UVLO (Under Voltage Lock Out) circuit is used to shut down the circuit when the voltage falls below approximately 3.3 V, while the TSD (Thermal Shutdown) circuit is used to shut down the circuit at a temperature of 175C and reset it at a temperature of 160C. u Overcurrent protection circuit (OCP) This function is used to detect a current passing through the power transistor FET with the CURRENT SENSE and activate the overcurrent protection when the current reaches approximately 4 A. If the overcurrent protection is activated, switching will be turned OFF to discharge the SS pin capacitance.
7/16
Timing chart Startup sequence
Vcc
SS
SW
VOUT
Fig.20 Startup sequence
Normal operation
VdC
SW
Vo
Io
Fig.21 While in normal operation
8/16
External component setting procedure (1) Setting of output L constant The coil L used for output is determined according to the rated current ILR and the maximum load current value IOMAX of the coil.
IL
Adjust so that (IOMAX + DIL) will not conflict with the rating.
VCC
ILR
Average IOMAX current
IL L VO CO
t
Fig.22
Fig.23
Adjust so that (IOMAX + DIL) will not conflict with the rating. At this time, DIL can be obtained according to the formula shown below.
VO 1 1 (VCC - VO) VCC L f
Step-down DIL =
[A] . . . (1.1)
,where f: Switching frequency
Furthermore, since the coil L value may also vary by approximately 30%, set this value with an adequate margin. If the coil current IL exceeds the rated coil current ILR, the internal IC element may be damaged. It is recommended to make setting of coil value in the range of 4.7 F to 100 F. (2) Setting of output Co constant For output capacitor, select the allowable ripple voltage VPP or the allowable drop voltage at a sharp change of load, whichever larger for the capacitor. The output ripple voltage can be obtained according to the formula shown below.
Step-down DVPP = DIL RESR + DIL VO 1 2CO VCC f [V] ,where f: Switching frequency
Design the component so that this constant will fall within the allowable ripple voltage. Furthermore, estimate the drop voltage VDR at a sharp change of load according to the formula shown below.
VDR = DI 10sec CO [V]
However, 10 sec will be the estimated value of the DC/DC converter response speed. Make setting of capacitance with thorough consideration given to the margin so that these two values will fall into the specified values. It is recommended to make setting of the capacitance in the range of 10 F to 100 F. if a short circuit occurs, an inverse current passes through the parasitic diode to cause damage to the internal circuits. To prevent that, insert a backflow prevention diode.
9/16
(3) Setting of feedback resistance constant In order to make settings of feedback resistance, refer to the formula shown. It is recommended to make setting of resistance in the range of 10 k to 330 k. Setting the resistance to 10 k or less will result in degraded power efficiency, while setting it to 330 k or more will increase the offset voltage due to the input bias current of 0.4 A (TYP) of the internal error amplifier.
VO Internal reference voltage: 0.6 V R8
FB R9
Fig.24
VO= R8+R9 0.6 [V] R9
(4) Setting of oscillation frequency Connecting a resistor to the RT pin (pin 4) will allow for the setting of triangular wave oscillation frequency. The RT determines the charge/discharge current to the internal capacitor, with which the frequency varies. Referring to Figure shown below, make settings of the RT resistor. Recommended setting range is 10 to 100 k. Be noted that any setting outside of this range may turn OFF switching, thus impairing the operation guarantee.
SWITCHING FREQUENCY : FSW [kHz] 100000
10000
1000
100
10
10 100 TIMING RESISTANCE : RT [k]
Fig.25 RT vs. Switching frequency (5) Setting of soft start time The soft start function will be required to prevent an excessive increase in the coil current and overshoot of the output voltage, while in startup operation. Figure below shows the relationship between the capacitor and the soft start time. Referring to this Figure, make the capacitor setting.
100
DELAY TIME : TV01 [ms]
10
1
0 0.01
0.10 SS CAPACITOR : CSS [F]
1.00
Fig.26 SS capacitance vs. Delay time It is recommended to make setting of capacitance value in the range of 0.01 to 10 F. Setting the capacitance value to 0.01 F or less may cause overshoot to the output voltage. If any startup-related function (sequence) of other power supply is provided, use a high-accuracy product (e.g. 5R) or the like. Furthermore, since the soft start time varies with the input voltage, output voltage, load, coil, output capacitor, or else, be sure to check to be sure this soft start time on the actual system.
10/16
(6) Phase compensation Phase compensation setting procedure The phase compensation setting procedure varies with the selection of capacitance used for DC/DC converter application. In this connection, the following section describes the procedure by classifying into the two types. Furthermore, the application stability conditions are described in the "Description" section. 1. Application stability conditions 2. For output capacitors having high ESR, such as electrolytic capacitor 3. For output capacitors having low ESR, such as ceramic capacitor or OS-CON
About application stability conditions The following section shows the stability conditions of negative feedback system. u At a 1 (0-dB) gain, the phase delay is 150 or less (i.e., the phase margin is 30 or more). Furthermore, since the DC/DC converter application is sampled according to the switching frequency, GBW of the overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted characteristics of this application. u At a 1 (0-dB) gain, the phase delay is 150 or less (i.e., the phase margin is 30 or more). u The GBW (i.e., frequency at 0-dB gain) for this occasion is 1/10 or less of the switching frequency. Consequently, in order to upgrade the responsiveness, higher switching frequency should be provided. A knack for ensuring the stability through the phase compensation is to cancel a secondary phase delay (-180) resulting from LC resonance with a secondary phase lead (i.e., through inserting two phase leads). Furthermore, the GBW (i.e., frequency at 0-dB gain) is determined according to phase compensation capacitance to be provided for the error amplifier. Consequently, in order to reduce the GBW, increase the capacitor capacitance.
(1) Typical (sun) integrator (Low pass filter) (2) Open loop characteristics of integrator (a) -20dB/decade
A Feed back R A FB Gain [dB] 0 C Phase [deg] 0 -90
GBW(b)
-90
Fig.27
-180
-180
Fig.28
Point (a) fa= 1 1.25 [Hz] 2pRCA 1 [Hz] 2pRC
Point (b) fa= GBW
Since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. In the case of the DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
11/16
For output capacitors having high ESR, such as aluminum electrolytic capacitor For output capacitors having high ESR (i.e., several ohms), the phase compensation setting procedure becomes comparatively simple. Since the DC/DC converter application has surely a LC resonant circuit attached to the output, a -180 phase-delay occurs in that area. If ESR component is present there, however, a +90 phase-lead occurs to shift the phase delay to -90. Since the phase delay is desired to set within 150, this is a very effective method but has a demerit to increase the ripple component of the output voltage.
(3) LC resonant circuit VCC (4) With ESR provided VCC
L C
VO
L RESR C
VO
fr=
1 [Hz] 2p LC
fr=
1 [Hz]: Resonance point 2p LC 1 [Hz]: Phase lead 2pRESRC
At this resonance point, a -180 phase-delay occurs.
fESR=
A -90 phase-delay occurs.
Fig.29
Fig.30
According to changes in phase characteristics due to the ESR, only one phase lead should be inserted. For this phase lead, select either of the methods shows below.
(5) Insert feedback resistance in the C. VO R1 A R2 FB R2 C1 C2 (6) Insert the R3 in integrator. VO R1 A FB R3 C2
Phase lead: fZ=
1 [Hz] 2pC1R1
Phase lead: fZ=
1 [Hz] 2pC2R3
Fig.31
Fig.32
For the purpose of canceling the LC resonance, the frequency to insert the phase lead should be set close to the LC resonant frequency. For output capacitors having low ESR, such as ceramic capacitor or OS-CON Unlike the section above, in order to use capacitors having low ESR (i.e., several tens of mW), two phase-leads should be inserted so that a -180 phase-delay due to LC resonance will be observed. Example (7) blow shows a typical phase compensation procedure.
(7) Phase compensation with secondary phase lead VO R1 A R2 FB Phase lead: fZ2= C1 R3 C2 Phase lead: fZ1= 1 [Hz] 2pR1C1 1 [Hz] 2pR3C2 1 2p LC [Hz]
LC resonant frequency: fr=
Fig.33 For the settings of phase lead frequency, insert both of the phase leads close to the LC resonant frequency.
12/16
Equivalent circuit
2.COMP1 11.COMP2
VREG
Vcc
3.FB1 10.FB2
VREG
20 5k
1k
2.5k 5k
4.RT
VREG
6.SS1/SDWN 8.SS2/SDWN
Vcc
2k 170 50 100k
14.SW2L 25.SW1L
PVcc
15.SW2 16.SW2 23.SW1 24.SW1 PVcc BOOT
17.BOOT2 22.BOOT1 10
SW
Fig.34 Equivalent circuit
13/16
Cautions on use 1) Absolute maximum ratings Even though thorough attention is exerted to the quality control of this IC, exceeding the absolute maximum ratings, such as applied voltage, operating temperature range, etc., can break down the IC. Should the IC break down, it will be impossible to identify breaking mode such as short circuit mode or an open mode. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including use of fuses, etc. GND potential GNDMake setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Thermal design With consideration given to power dissipation (Pd) in the actual use state, provide the thermal design with an adequate margin. Short circuit between pins and erroneous mounting In order to mount ICs on a set printed circuit board, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between pins or between the pin and the power supply or the GND pin, the ICs can break down. Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. Inspection with set printed circuit board On the inspection with the set printed circuit board, if a capacitor is connected to a low-impedance pin, the IC can suffer stress. Therefore, be sure to discharge from the set printed circuit board by each process. For protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set printed circuit board. Furthermore, in order to connect the jig for the inspection process, be sure to turn OFF the power supply and then mount the set printed circuit board to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount the set printed circuit board from the jig. IC pin input This IC is a monolithic IC, which has P+ isolation and P layer between elements to isolate the elements. P-N junction is formed with this P layer and the N layer of each element, thus composing a variety of parasitic elements. For example, as shown in Fig. 35, if the resistor and the transistor is connected with the pin respectively, When GND>(Pin A) for the resistor or GND>(Pin B) for the transistor (NPN), P-N junction will operate as a parasitic diode. For the transistor (NPN), when GND>(Pin B), the parasitic NPN transistor will operate with the N layer of other element in the proximity of the said parasitic diode. In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the IC. Therefore, pay thorough attention not to handle the input pins such as to apply to the input pins a voltage lower than the GND (P layer) so that any parasitic element will operate.
Resistor
(Pin A) (Pin B) C
2)
3)
4)
5)
6)
7)
Transistor (NPN)
B E
GND N P+ N P layer P N P+ N Parasitic element GND Parasitic element (Pin B) Parasitic element N P layer GND P+ N N P P+
(Pin A)
B
C E
GND
GND Parasitic element
Fig.35 Typical simple construction of monolithic IC
14/16
8)
Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. On the application shown on the right, if the VCC and each output voltage are inverted, for example, if the VCC is short-circuited to the Ground with external diode charged, internal circuits or elements may be damaged. To avoid that, use the output pin capacitor in the range of 10 to 100 F. Furthermore, in order to use a capacitor of 100 F or more, it is recommended to insert a backflow prevention diode or a bypass diode between the output and VCC.
Bypass diode Backflow prevention diode
VCC
Output pin
9)
Fig.36 Typical bypass diode application
10) Overcurrent protection circuit Output has a built-in overcurrent protection circuit according to the current capability, which prevents the destruction of the IC at short-circuiting of load. However, this protection circuit is only effective to prevent destruction due to a sudden accident but does not support for the continuous operation of the protection circuit or use in transition. Furthermore, since the current capability has characteristic negative to temperature, give consideration to the thermal design. 11) Temperature protection circuit This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above, be sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range continues, the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output power element. Then, when the tip temperature Tj falls, the circuit will be automatically reset. Furthermore, since the temperature protection circuit is activated under the condition exceeding the absolute maximum ratings, NEVER attempt to use the temperature protection circuit for set design or else. 12) Input capacitor In order to derate a peak noise, which occurs while in switching operation, be sure to insert a capacitor (ceramic capacitor) having a low ESR of 10 to 100 F as close to the pin as possible between the VCC and Ground.
Power dissipation
1500 Power dissipation : PD [mW] 1250 1000 750 500 250 0
0
25
50
75
100
125
150
Ambient temperature : Ta [C]
Fig.37 Thermal derating characteristics
15/16
Selection of order type
B
D
9
3
0
2
F
P
-
E
2
Product name
Package/Forming specifications
Package specifications HSOP25
13.60.2 2.750.1 7.80.3 5.40.2 0.3 Min.
25 14

Package style Embossed carrier tape Q'ty per package 2000 pcs Packaging E2 (When holding a reel by left hand and pulling out the tape by direction
right hand, No. 1 pin appears in the upper left of the reel.)
1
13
1.90.1
1.950.1
0.250.1
0.11
0.8 0.360.1
0.1
Reel (Unit : mm)
No. 1 pin
Pulling-out side
* Please place an order for this IC in multiplies of the quantity per package.
The contents described herein are correct as of December, 2008
Catalog No. 08T907A '08.12 ROHM(c)
Appendix
Notes
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Appendix1-Rev3.0

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